Semiconductor device

ABSTRACT

One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation application of U.S. patent application Ser. No. 14/779,961, filed on Sep. 24, 2015, which is based upon and claims the benefit of priority from PCT Publication Number PCT/JP2014/057671, filed on Mar. 20, 2014, and Japan patent application No. 2013-063818, filed on Mar. 26, 2013, all of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present invention relates to a semiconductor device.

BACKGROUND

In order to increase the density of semiconductor devices, a plurality of semiconductor chips are stacked one over another. Such a semiconductor device is sometimes known as an MCP (Multi Chip Package).

The structure of MCP-type semiconductor devices is normally one in which an upper-level semiconductor chip is cross-stacked relative to a lower-level semiconductor chip to allow for wire bonding.

For example, patent literature article 1 discloses an MCP semiconductor device in which a rectangular second semiconductor chip (upper-level semiconductor chip) is stacked on a rectangular first semiconductor chip (lower-level semiconductor chip) installed on a wiring substrate, in a state in which the second semiconductor chip is rotated through 90° relative to the first semiconductor chip (patent literature article 1).

PATENT LITERATURE

Patent literature article 1: Japanese Patent Kokai 2011-86943

SUMMARY OF THE INVENTION Problems to be Resolved by the Invention

However, if the semiconductor chips are cross-stacked, as in patent literature article 1, the thickness of the sealing resin on the lower-level semiconductor chip is different from the thickness of the sealing resin on the upper-level semiconductor chip, and therefore the side of the lower-level semiconductor chip on which the short edge, having the greater thickness of sealing resin, is disposed warps to a greater extent than the side of the upper-level semiconductor chip on which the short edge is disposed, and this gives rise to a problem in that the semiconductor device becomes warped in the shape of a saddle.

If the semiconductor device becomes warped in the shape of a saddle in this way, then there is a risk that secondary mounting of the semiconductor device on a mother board, or secondary mounting of the semiconductor device on a lower package in a PoP (Package on Package) cannot be performed satisfactorily.

There is therefore a desire for a semiconductor device having a structure capable of suppressing warping even if semiconductor chips are stacked on one another.

Means of Overcoming the Problems

In a first aspect of the present invention, a semiconductor device comprises: a wiring substrate; a first semiconductor chip installed on one surface of the wiring substrate; a second semiconductor chip stacked on the first semiconductor chip in such a way that a portion of a surface of the first semiconductor chip is exposed; a warp regulating member installed on the exposed portion of the surface; and a sealing body formed on the wiring substrate in such a way as to cover the first semiconductor chip, the second semiconductor chip and the warp regulating member.

Advantages of the Invention

According to the present invention, it is possible to provide a semiconductor device having a structure capable of suppressing warping even if semiconductor chips are stacked on one another.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is plan view illustrating a semiconductor device 200 according to a first mode of embodiment, in which only a portion of a sealing body 220 is depicted.

FIG. 2 is a cross-sectional view through A-A′ in FIG. 1.

FIG. 3 is a cross-sectional view through B-B′ in FIG. 1.

FIG. 4 is a drawing illustrating a procedure for manufacturing the semiconductor device 200.

FIG. 5 is a drawing illustrating a procedure for manufacturing the semiconductor device 200.

FIG. 6 is plan view illustrating a semiconductor device 200 a according to a second mode of embodiment, in which only a portion of the sealing body 220 is depicted.

FIG. 7 is a cross-sectional view through A-A′ in FIG. 6.

FIG. 8 is a cross-sectional view through B-B′ in FIG. 6.

FIG. 9 is plan view illustrating a semiconductor device 200 b according to a third mode of embodiment, in which only a portion of the sealing body 220 is depicted.

FIG. 10 is a cross-sectional view through A-A′ in FIG. 9.

FIG. 11 is a cross-sectional view through B-B′ in FIG. 9.

FIG. 12 is a drawing illustrating a procedure for manufacturing the semiconductor device 200 b.

FIG. 13 is a drawing illustrating a procedure for manufacturing the semiconductor device 200 b.

MODES OF EMBODYING THE INVENTION

Preferred modes of embodiment of the present invention will now be described in detail with reference to the drawings.

The general structure of the semiconductor device 200 according to the first embodiment of the present invention will first be described with reference to FIG. 1 to FIG. 3.

Here, a semiconductor memory in which a memory chip is installed is illustrated as the semiconductor device 200, by way of example.

As illustrated in FIG. 1 to FIG. 3, the semiconductor device 200 comprises: a wiring substrate 201; a first semiconductor chip 203 installed on one surface of the wiring substrate 201; a second semiconductor chip 205 stacked on the first semiconductor chip 203 in such a way that portions of a surface of the first semiconductor chip 203 are exposed to form exposed surfaces 210 a and 210 b; silicon substrates 211 a and 211 b, serving as warp regulating members, installed on the exposed surfaces 210 a and 210 b; and a sealing body 220 formed on the wiring substrate 201 in such a way as to cover the first semiconductor chip 203, the second semiconductor chip 205 and the silicon substrates 211 a and 211 b.

More specifically, the semiconductor device 200 comprises: the wiring substrate 201 having on one surface a plurality of connection pads 223 a, 223 b, 223 c and 223 d; the first semiconductor chip 203 which is installed on one surface of the wiring substrate 201 and has electrode pads 103 a and 103 b; the second semiconductor chip 205 which is stacked on the first semiconductor chip 203 and has electrode pads 107 a and 107 b; the silicon substrates 211 a and 211 b which are installed on the exposed surfaces 210 a and 210 b; a plurality of wires 215 electrically connecting the plurality of connection pads 223 a and 223 c to the electrode pads 103 a and 103 b; a plurality of wires 217 electrically connecting the plurality of connection pads 223 b and 223 d to the electrode pads 107 a and 107 b; and the sealing body 220, formed on the one surface of the wiring substrate 201 in such a way as to cover the first semiconductor chip 203, the second semiconductor chip 205, the silicon substrates 211 a and 211 b, and the wires 215 and 217.

The semiconductor device 200 further comprises solder balls 216, serving as external terminals for connecting the semiconductor device 200 to an external device.

Details of the members which form the semiconductor device 200 according to the first mode of embodiment of the present invention will next be described with reference to FIG. 1 to FIG. 3.

The wiring substrate 201 comprises, for example, an insulating substrate 219 formed from a substantially quadrilateral plate-shaped glass epoxy or the like, wiring line layers (which are not shown in the drawings) which are pattern-formed on both surfaces of the insulating substrate 219, and insulating films 221 formed in such a way as to cover the wiring line layers. The plurality of connection pads 223 a, 223 b, 223 c and 223 d are connected to the wiring line layer on one surface side of the wiring substrate 201. Further, a plurality of land portions 225 are connected to the wiring line layer on the other surface side of the wiring substrate 201. As illustrated in FIG. 1, the plurality of connection pads 223 a, 223 b, 223 c and 223 d are respectively aligned in the vicinity of the peripheral edge portions of the four sides which form a quadrilateral constituting the one surface of the wiring substrate 201. Further, the plurality of land portions 225 are disposed in a lattice formation on the other surface of the wiring substrate 201.

Meanwhile, the plurality of connection pads 223 a, 223 b, 223 c and 223 d and the plurality of land portions 225 are connected to one another by means of wiring lines connected thereto and vias or the like which penetrate through the insulating substrate 219.

The wires 215 are connected to the connection pads 223 a and 223 c, the wires 217 are connected to the connection pads 223 b and 223 d, and the solder balls 216 are installed on the land portions 225.

The insulating film 221 is a solder resist (SR) or the like. The insulating film 221 is formed over the entire surface of the wiring substrate 201, excluding certain pre-determined regions. In other words, a portion of the insulating film 221 is removed in certain regions to provide one or more opening portions. For example, opening portions 235 a, 235 b, 235 c and 235 d are formed on one surface side of the wiring substrate 201. The opening portions 235 a, 235 b, 235 c and 235 d expose regions in which the plurality of connection pads 223 a, 223 b, 223 c and 223 d are formed, and regions in the vicinity thereof.

Opening portions exposing each of the plurality of land portions 225 are also formed on the other surface side of the wiring substrate 201.

The first semiconductor chip 203 is a substantially quadrilateral (here, rectangular) plate-shaped memory chip, and certain circuits and the electrode pads 103 a and 103 b are formed on one surface side thereof. The plurality of electrode pads 103 a and 103 b are aligned along the short edges 212 a and 212 b of the rectangle of the first semiconductor chip 203. The other surface of the first semiconductor chip 203 is adhesively secured by means of the adhesive member 105, such as a DAF (Die Attached Film), to a region of the wiring substrate 201 in which the insulating film 221 is formed.

In the same way as with the first semiconductor chip 203, the second semiconductor chip 205 is a substantially quadrilateral (rectangular) plate-shaped memory chip, and circuits similar to those on the first semiconductor chip 203, and the electrode pads 107 a, 107 b, are formed on one surface side thereof. The plurality of electrode pads 107 a and 107 b are formed aligned along the short edges 206 a and 206 b of the rectangle of the second semiconductor chip 205.

The second semiconductor chip 205 is installed by being stacked on the first semiconductor chip 203.

The second semiconductor chip 205 is formed in such a way that long edges 214 a and 214 b thereof face the short edges 212 a and 212 b of the first semiconductor chip 203, in such a way that the regions in which the electrode pads 103 a and 103 b of the first semiconductor chip 203 are formed are not covered. More specifically, the second semiconductor chip 205 is disposed (cross-stacked) in such a way that its planar arrangement intersects that of the first semiconductor chip 203, in a state in which the second semiconductor chip 205 is rotated through 90° relative to the first semiconductor chip 203.

As a result, the short edges 206 a and 206 b of the second semiconductor chip 205 overhang from the first semiconductor chip 203. In this way, portions of the upper surface of the first semiconductor chip 203 are exposed away from the second semiconductor chip 205, to form the exposed surfaces 210 a and 210 b.

The other surface of the second semiconductor chip 205 is adhesively secured to the first semiconductor chip 203 by means of the adhesive member 105 such as a DAF.

It should be noted that the second semiconductor chip 205 is preferably formed with a chip thickness that is greater than the chip thickness of the first semiconductor chip 203. This is to make it possible for the electrode pads 107 a and 107 b on the second semiconductor chip 205 to be connected satisfactorily using wires to the wiring substrate 201, without the occurrence of chip cracks, even if the second semiconductor chip 205 overhangs from the first semiconductor chip 203.

The silicon substrates 211 a and 211 b are members which prevent warping of the first semiconductor chip 203, and they are installed on the first semiconductor chip 203 with the interposition of the adhesive members 105.

The silicon substrates 211 a and 211 b are disposed on the exposed surfaces 210 a and 210 b, in regions thereof between the electrode pads 103 a and 103 b and the second semiconductor chip 205, in such a way that the electrode pads 103 a and 103 b on the first semiconductor chip 203 are exposed.

The silicon substrates 211 a and 211 b are preferably formed with substantially the same thickness as the second semiconductor chip 205, which is the upper-level memory chip.

In this way, by installing the silicon substrates 211 a and 211 b on the first semiconductor chip 203, which is the lower-level memory chip, exposed away from the second semiconductor chip 205, which is the upper-level memory chip, the thickness of the sealing body 220 formed on the exposed surfaces 210 a and 210 b of the first semiconductor chip 203, exposed away from the second semiconductor chip 205, can be made to be the same as or close to the thickness of the sealing body 220 formed on the second semiconductor chip 205.

In this way, warping of the first semiconductor chip 203 along the short edges 212 a and 212 b can be suppressed, and warping of the semiconductor device 200 can be reduced. Further, by reducing warping of the semiconductor device 200, secondary mounting of the semiconductor device 200 onto a motherboard or a lower package can be performed satisfactorily.

Meanwhile, the wires 215 and 217 are formed from an electrically conductive metal such as Au or Cu. The wires 215 and 217 electrically connect the plurality of electrode pads 103 a, 103 b, 107 a and 107 b to the corresponding connection pads 223 a, 223 b, 223 c and 223 d.

Here, the wires 215 connect the electrode pads 103 a and 103 b to the connection pads 223 a and 223 c, and the wires 217 connect the electrode pads 107 a and 107 b to the connection pads 223 b and 223 d.

The sealing body 220 is an insulating resin such as a thermosetting epoxy resin, and it seals the first semiconductor chip 203, the second semiconductor chip 205, the silicon substrates 211 a and 211 b and the wires 215 and 217 in such a way as to cover one surface side of the wiring substrate 201.

Details of the members which form the semiconductor device 200 have been provided hereinabove.

A method of manufacturing the semiconductor device 200 will next be described with reference to FIG. 4 and FIG. 5.

First, a wiring mother substrate 300 as illustrated in FIG. 4 (a) is prepared. The wiring mother substrate 300 has a plurality of product-forming portions 301 disposed in a matrix formation, each product-forming portion 301 corresponding to a wiring substrate 201.

Next, as illustrated in FIG. 4(b), the wiring mother substrate 300 is conveyed to a die bonding device, which is not shown in the drawings, and the first semiconductor chips 203 are installed on the product-forming portions 301 of the wiring mother substrate 300 using the die bonding device.

The first semiconductor chips 203 are installed in such a way that the short edges 212 a and 212 b on which the electrode pads 103 a and 103 b are provided face the connection pads 223 a and 223 c. The first semiconductor chips 203 are adhesively secured to the wiring mother substrate 300 by means of the adhesive members 105 such as a DAF or the like, provided on the other surface.

Next, as illustrated in FIG. 4(c), the second semiconductor chips 205 are installed on the first semiconductor chips 203 using the die bonding device.

More specifically, the second semiconductor chips 205 are stacked in a state in which they are rotated through 90° relative to the first semiconductor chips 203, in such a way that the electrode pads 103 a and 103 b and the exposed surfaces 210 a and 210 b (see FIG. 1) are exposed.

By stacking the second semiconductor chips 205 in a state in which they are rotated through 90° relative to the first semiconductor chips 203, the plurality of electrode pads 103 a and 103 b formed along the short edges 212 a and 212 b of the first semiconductor chips 203 are exposed away from the second semiconductor chips 205.

Next, as illustrated in FIG. 4(d), the silicon substrates 211 a and 211 b are installed on the exposed surfaces 210 a and 210 b of the first semiconductor chips 203.

The silicon substrates 211 a and 211 b are installed using the die bonding device or the like.

Next, as illustrated in FIG. 4(e), the electrode pads 103 a and 103 b on the first semiconductor chips 203 are connected to the corresponding connection pads 223 a and 223 c by means of the wires 215, and the electrode pads 107 a and 107 b on the second semiconductor chips 205 are connected to the connection pads 223 b and 223 d by means of the wires 217 (see FIG. 1). A wire bonding device, which is not shown in the drawings, can be employed to form the connections using the wires 215 and 217. The connections are formed, for example, by means of ball bonding using an ultrasonic thermo-compression bonding method. More specifically, the distal ends of the wires 215, which have been melted to form balls, are bonded onto the electrode pads 103 a and 103 b using ultrasonic thermo-compression bonding, and the rear ends of the wires 215 are bonded onto the corresponding connection pads 223 a and 223 c using ultrasonic thermo-compression bonding in such a way that the wires 215 describe a certain loop shape.

Similarly, the distal ends of the wires 217, which have been melted to form balls, are bonded onto the electrode pads 107 a and 107 b using ultrasonic thermo-compression bonding, and the rear ends of the wires 217 are bonded onto the corresponding connection pads 223 b and 223 d using ultrasonic thermo-compression bonding in such a way that the wires 217 describe a certain loop shape.

Next, the sealing body 220 is formed on one surface side of the wiring mother substrate 300 by batch molding using a molding device, as illustrated in FIG. 5(a).

More specifically, the wiring mother substrate 300 is placed in a molding device, which is not shown in the drawings, and in a state in which the wiring mother substrate 300 is clamped between an upper die and a lower die of the molding device, the mold is filled with molten sealing resin, for example a thermosetting resin such as an epoxy resin, which is cured in the filled state.

The sealing resin is thus thermally cured to form the sealing body 220 covering collectively the product-forming portions 301, as illustrated in FIG. 5(a).

The wiring mother substrate 300 is then removed from the molding device and is subjected to reflow at a certain temperature, thereby completely curing the sealing body 220.

Next, as illustrated in FIG. 5(b), the solder balls 216 are installed on each of the land portions 225 on the other surface side of the wiring mother substrate 300.

More specifically, using a suction-attachment mechanism, which is not shown in the drawings, in which a plurality of suction-attachment holes are formed matching the arrangement of the land portions 225 on the wiring mother substrate 300, for example, the solder balls 216 are held in the suction-attachment holes, and the held solder balls 216 are installed collectively on the land portions 225 of the wiring mother substrate 300, with the interposition of flux.

After the solder balls 216 have been installed on all of the product-forming portions 301, the solder balls 216 are secured by subjecting the wiring mother substrate 300 to reflow.

Next, as illustrated in FIG. 5(c), the sealing body 220 is caused to adhere to a dicing tape 251, and the sealing body 220 and the wiring mother substrate 300 are supported by the dicing tape 251. Then using a dicing blade, which is not shown in the drawings, the wiring mother substrate 300 and the sealing body 220 are cut lengthwise and crosswise along dicing lines 234 (see FIG. 4(a)). By this means the wiring mother substrate 300 is diced into individual product-forming portions 301. The diced product-forming portions 301 and sealing bodies 220 are then picked up from the dicing tape 251 to yield the semiconductor devices 200 such as those illustrated in FIG. 1.

Thus, according to the first mode of embodiment, the semiconductor device 200 comprises: the wiring substrate 201; the first semiconductor chip 203 installed on one surface of the wiring substrate 201; the second semiconductor chip 205 stacked on the first semiconductor chip 203 in such a way that portions of the surface of the first semiconductor chip 203 are exposed to form the exposed surfaces 210 a and 210 b; the silicon substrates 211 a and 211 b, installed on the exposed surfaces 210 a and 210 b; and the sealing body 220 formed on the wiring substrate 201 in such a way as to cover the first semiconductor chip 203, the second semiconductor chip 205 and the silicon substrates 211 a and 211 b.

Thus the thickness of the sealing body 220 formed on the exposed surfaces 210 a and 210 b of the first semiconductor chip 203, exposed away from the second semiconductor chip 205, can be made to be the same as or close to the thickness of the sealing body 220 formed on the second semiconductor chip 205.

In this way, warping of the first semiconductor chip 203 along the short edges 212 a and 212 b can be suppressed, and warping of the semiconductor device 200 can be reduced. Further, by reducing warping of the semiconductor device 200, secondary mounting of the semiconductor device 200 onto a mother board or a lower package can be performed satisfactorily.

A second mode of embodiment will now be described with reference to FIG. 6 to FIG. 8.

In the second mode of embodiment, the second semiconductor chip 205 in the first mode of embodiment is installed shifted in such a way as to be adjacent to one set of the electrode pads 103 a or 103 b on the first semiconductor chip 203.

It should be noted that in the second mode of embodiment, the same numbers denote elements that fulfill the same function as in the first embodiment, and the description will mainly relate to parts that differ from the first mode of embodiment.

As illustrated in FIG. 6 to FIG. 8, in a semiconductor device 200 a according to the second mode of embodiment, the second semiconductor chip 205 is installed shifted in such a way as to be adjacent to one set of the electrode pads 103 a or 103 b (here, the side closest to the electrode pads 103 a) on the first semiconductor chip 203.

The surface areas of the exposed surface 210 a and the exposed surface 210 b thus differ significantly, the surface area of the exposed surface 210 a being the minimum surface area required to expose the electrode pads 103 a.

Therefore one silicon substrate 211 c is installed, on only the exposed surface 210 b.

Thus warp regulating members do not necessarily need to be disposed on both exposed surfaces 210 a and 210 b, and depending on the surface areas of the exposed surfaces 210 a and 210 b, the silicon substrate 211 c may be installed on only one exposed surface.

This makes it possible for the number of silicon substrates 211 c installed to be reduced compared with the first mode of embodiment.

Thus, according to the second mode of embodiment, the semiconductor device 200 a comprises: the wiring substrate 201; the first semiconductor chip 203 installed on one surface of the wiring substrate 201; the second semiconductor chip 205 stacked on the first semiconductor chip 203 in such a way that portions of the surface of the first semiconductor chip 203 are exposed to form the exposed surfaces 210 a and 210 b; the silicon substrate 211 c, installed on the exposed surface 210 b; and the sealing body 220 formed on the wiring substrate 201 in such a way as to cover the first semiconductor chip 203, the second semiconductor chip 205 and the silicon substrate 211 c.

This mode of embodiment therefore exhibits the same advantages as the first mode of embodiment.

Further, according to the second mode of embodiment, the second semiconductor chip 205 is installed shifted in such a way as to be adjacent to the electrode pads 103 a on the first semiconductor chip 203, and one silicon substrate 211 c is installed, on only the exposed surface 210 b.

This makes it possible for the number of silicon substrates 211 c installed to be reduced compared with the first mode of embodiment.

A third mode of embodiment will now be described with reference to FIG. 9 to FIG. 13.

In the third mode of embodiment, highly-resilient bodies 213 a and 213 b are used as the warp regulating members in the first mode of embodiment.

It should be noted that in the third embodiment, the same numbers denote elements that fulfill the same function as in the first embodiment, and the description will mainly relate to parts that differ from the first embodiment.

The configuration of a semiconductor device 200 b according to the third mode of embodiment will first be described.

As illustrated in FIG. 9 to FIG. 11, in the semiconductor device 200 b according to the third mode of embodiment, the highly-resilient bodies 213 a and 213 b are provided as the warp regulating members on the exposed surfaces 210 a and 210 b.

A resin material having a modulus of elasticity higher than that of the sealing body 220, specifically an insulating paste material or the like, is, for example, employed as the material used to form the highly-resilient bodies 213 a and 213 b.

Further, the highly-resilient bodies 213 a and 213 b cover the electrode pads 103 a and 103 b and the portions of the wires 215 connected to the electrode pads 103 a and 103 b.

Thus the warp regulating members do not necessarily need to be bulk materials such as silicon substrates, and resin or the like may also be employed.

By adopting such a configuration, it is possible for the highly-resilient bodies 213 a and 213 b to cover the electrode pads 103 a and 103 b and the portions of the wires 215 connected to the electrode pads 103 a and 103 b, and it is therefore possible to suppress wire sweep and wire short circuiting of the wires 215. It should be noted that the highly-resilient bodies 213 a and 213 b are preferably formed with substantially the same thickness as the second semiconductor chip 205, in the same way as with the silicon substrates 211 a, 211 b and 211 c.

A method of manufacturing the semiconductor device 200 b will now be described briefly.

First, in the same way as in the first mode of embodiment, the wiring mother substrate 300 illustrated in FIG. 12(a) is prepared, then as illustrated in FIG. 12(b) the wiring mother substrate 300 is conveyed to a die bonding device, which is not shown in the drawings, and the first semiconductor chips 203 are installed on the product-forming portions 301 of the wiring mother substrate 300 using the die bonding device, after which, as illustrated in FIG. 12(c), the second semiconductor chips 205 are installed on the first semiconductor chips 203.

Next, as illustrated in FIG. 12(d), wire bonding is employed to connect the first semiconductor chips 203 and the second semiconductor chips 205 to the wiring substrates 201 using the wires 215 and 217.

Next, as illustrated in FIG. 12(e), the highly-resilient bodies 213 a and 213 b are formed on the exposed surfaces 210 a and 210 b.

More specifically, an insulating paste material is supplied onto the exposed surfaces 210 a and 210 b using a dispenser, which is not shown in the drawings, for example.

At this time, the highly-resilient bodies 213 a and 213 b preferably cover the electrode pads 103 a and 103 b and the portions of the wires 215 connected to the electrode pads 103 a and 103 b.

In the same way as in the first mode of embodiment, the semiconductor device 200 b is obtained by subsequently forming the sealing body 220 illustrated in FIG. 13(a), installing the solder balls 216 illustrated in FIG. 13(b), and cutting (dicing) the wiring mother substrate 300 as illustrated in FIG. 13(c).

Thus, according to the third mode of embodiment, the semiconductor device 200 b comprises: the wiring substrate 201; the first semiconductor chip 203 installed on one surface of the wiring substrate 201; the second semiconductor chip 205 stacked on the first semiconductor chip 203 in such a way that portions of the surface of the first semiconductor chip 203 are exposed to form the exposed surfaces 210 a and 210 b; the highly-resilient bodies 213 a and 213 b, installed on the exposed surfaces 210 a and 210 b; and the sealing body 220 formed on the wiring substrate 201 in such a way as to cover the first semiconductor chip 203, the second semiconductor chip 205 and the highly-resilient bodies 213 a and 213 b. This mode of embodiment therefore exhibits the same advantages as the first mode of embodiment.

Further, according to the third mode of embodiment, the highly-resilient bodies 213 a and 213 b are provided as the warp regulating members, and the highly-resilient bodies 213 a and 213 b cover the electrode pads 103 a and 103 b and the portions of the wires 215 connected to the electrode pads 103 a and 103 b.

Thus in comparison with the first mode of embodiment, wire sweep and wire short circuiting of the wires 215 can also be suppressed.

INDUSTRIAL APPLICABILITY

The invention devised by the inventors has been described hereinabove with reference to modes of embodiment, but the present invention is not restricted to the abovementioned modes of embodiment, and it goes without saying that various modifications are possible without deviating from the gist of the invention.

For example, in the modes of embodiment described hereinabove, memory chips are illustrated as the semiconductor chips, by way of example, but any combination of semiconductor chips may be employed, for example logic chips and memory chips.

Further, in the modes of embodiment described hereinabove, a description is given of cases in which semiconductor chips are stacked on two levels, but the present invention is also applicable in the same way to semiconductor devices in which semiconductor chips are stacked on three or more levels, by disposing the warp regulating members on the semiconductor chip adjacent to and exposed away from the uppermost semiconductor chip.

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-63818, filed on Mar. 26, 2013, the entire disclosure of which is incorporated herein by reference.

EXPLANATION OF THE REFERENCE CODES

-   130 a, 103 b: Electrode pad -   105: Adhesive member -   107 a, 107 b: Electrode pad -   200: Semiconductor device -   200 a: Semiconductor device -   200 b: Semiconductor device -   201: Wiring substrate -   203: First semiconductor chip -   205: Second semiconductor chip -   206 a, 206 b: Short edge -   210 a, 210 b: Exposed surface -   211 a, 211 b, 211 c: Silicon substrate -   212 a, 212 b: Short edge -   213 a, 213 b: Resilient body -   214 a, 214 b: Long edge -   215: Wire -   216: Solder ball -   217: Wire -   219: Insulating substrate -   220: Sealing body -   221: Insulating film -   223 a, 223 b, 223 c, 223 d: Connection pad -   225: Land portion -   234: Dicing line -   235 a, 235 b, 235 c, 235 d: Opening portion -   251: Dicing tape -   300: Wiring mother substrate -   301: Product-forming portion 

What is claimed is:
 1. A semiconductor device comprising: a wiring substrate having connection pads; a first semiconductor chip installed on one surface of the wiring substrate, the first semiconductor chip having a first edge and a second edge opposite to the first edge; a second semiconductor chip stacked on the first semiconductor chip so that the second semiconductor chip crosses over the first edge and the second edge of the first semiconductor chip and a portion of a surface of the first semiconductor chip is exposed, wherein the second semiconductor chip is the top most semiconductor chip in the package; a plurality of electrode pads on the exposed portion of the first semiconductor chip, a plurality of wires connecting the electrode pads to the connection pads of the wiring substrate respectively, a warp regulating member disposed directly on the exposed portion of the surface, wherein the warp regulating member covers the entire exposed portion including the plurality of electrode pads; and a sealing body formed on the wiring substrate to cover the first semiconductor chip, the second semiconductor chip, and the warp regulating member, wherein a portion of the wire is wrapped by the warp regulating member, and the warp regulating member is in different material to the sealing body.
 2. The semiconductor device as claimed in claim 1, wherein the warp regulating member is a highly-resilient body having a modulus of elasticity higher than that of the sealing body.
 3. The semiconductor device as claimed in claim 1, wherein the first and second semiconductor chips have a rectangular planar shape and have a long edge and a short edge, and the second semiconductor chip is stacked on the first semiconductor chip so that the long edge of the second semiconductor chip faces the short edge of the first semiconductor chip.
 4. The semiconductor device as claimed in claim 1, further comprising external terminals disposed on another surface of the wiring substrate and electrically connected to the first semiconductor chip.
 5. The semiconductor device as claimed in claim 1, wherein the warp regulating member has an upper surface substantially aligned with as an upper surface of the second semiconductor chip.
 6. The semiconductor device as claimed in claim 1, wherein the warp regulating member is substantially aligned with the entire exposed portion in plan view.
 7. The semiconductor device as claimed in claim 3, wherein the second semiconductor chip is cross-stacked in a state rotated relative to the first semiconductor chip so that the planar arrangements of the first semiconductor chip and the second semiconductor chip intersect.
 8. The semiconductor device as claimed in claim 3, wherein the first semiconductor chip has the electrode pads disposed along the short edge and electrically connected to the wiring substrate, and the second semiconductor chip is disposed adjacent to the electrode pads.
 9. The semiconductor device as claimed in claim 3, wherein the thickness of the second semiconductor chip is greater than the thickness of the first semiconductor chip.
 10. The semiconductor device as claimed in claim 4, wherein the external terminals are solder balls. 